Verification of Combinational Logic in Nuprl

http://techreports.library.cornell.edu:8081/Dienst/UI/1.0/Display/cul.cs/TR89-1018
unofficial copies [PDF], [PS]


by David A. Basin and Peter Del Vecchio

Hardware Specification Verification and Synthesis: Mathematical Aspects, LNCS 408, pp. 333-357, Springer-Verlag, (also Cornell TR 89-1018), 1989.

Abstract

We present a case study of hardware specification and verification in the Nuprl Proof Development System. Within Nuprl we have built a specialized environment consisting of tactics, definitions, and theorems for specifying and reasoning about hardware. Such reasoning typically consists of term-rewriting, case-analysis, induction, and arithmetic reasoning. We have built tools that provide high-level assistance for these tasks. The hardware component that we have proven is the front end of a floating-point adder/subtractor. This component, the MAEC (Mantissa Adjuster and Exponent Calculator), has 5459 transistors and has been proven down to the transistor level. As the circuit has 118 inputs and 107 outputs, verification by traditional methods such as case analysis would have been a practical impossibility.